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SystemC/TLM Modeling Engineer – Virtual Prototyping


Sector
Other research and experimental development on natural sciences and engineering
Contract
Full-time


Job Location

Job location, Kapeldreef 75
3001 HEVERLEE , Arrondissement of Leuven - Belgium

Job Description

Join imec’s Compute System Architecture (CSA) center of excellence as a Senior SystemC/TLM Modeling Engineer, where you will drive the development of advanced virtual platforms for next-generation compute systems. This role is ideal for candidates with deep, hands-on experience in SystemC and transaction-level modeling (TLM), who are passionate about architecture exploration, performance modeling, and enabling early hardware/software co-design.

What you will do

Lead the design, development, and integration of SystemC/TLM models for SoC architectures, memory controllers, interconnects, and custom IP blocks, enabling virtual prototyping and early system validation and performance modeling of future compute systems.
Develop and maintain reusable, interoperable SystemC models that integrate with industry-standard virtual platform tools and in-house frameworks.
Collaborate with hardware and software architects to define modeling requirements, validate system functionality, and support architecture exploration and design trade-off studies.
Develop and execute comprehensive testbenches for functional and performance verification of SystemC/TLM models, including debugging and root-cause analysis at the system level.
Document modeling methodologies, interfaces, and best practices to ensure model reusability and knowledge transfer across teams.

Who you are

Master’s or Doctoral degree in Computer Science, Electrical/Computer Engineering, or a related field.
5+ years of hands-on experience in SystemC and TLM modeling for complex SoC or system-level platforms in an industrial or research setting.
Deep expertise in C++ and SystemC, with a proven track record of developing, integrating, and optimizing TLM 2.0 models.
Strong background in computer architecture, microarchitecture, and hardware/software co-design.
Experience with RTL design (Verilog/SystemVerilog/VHDL) and integrating TLM with RTL for hybrid simulation environments is a plus.
Familiarity with standard hardware interfaces and protocols (e.g., AXI, NoC fabrics).
Proficiency with modern software engineering practices (version control, CI/CD, unit testing).
Excellent communication and collaboration skills; ability to work independently and as part of a cross-functional team.


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